The present disclosure relates to a semiconductor integrated circuit device using three-dimensional transistor devices such as fin field effect transistors (FETs) and nanowire FETs.
As a method for forming a semiconductor integrated circuit on a semiconductor substrate, the standard cell method is known. In the standard cell method, basic units having specific logical functions (e.g., an inverter, a latch, a flipflop, and a full adder) are prepared in advance as standard cells. A plurality of such standard cells are placed on a semiconductor substrate and connected to each other via interconnects, whereby an LSI chip is designed.
In recent years, use of FETs having a fin structure (hereinafter referred to as fin FETs) has been proposed in the field of semiconductor devices. FIG. 9 is a diagrammatic view showing an outline of a fin FET. Unlike a FET having a two-dimensional structure, the source and drain of the fin FET have a raised solid structure called a fin. A gate is placed to surround the fin. Having such a fin structure, where the channel region is formed of three faces of the fin, the controllability of the channel greatly improves compared to that of conventional ones. This brings about effects such as reduction in leakage power, improvement of ON current, and reduction in operating voltage, thereby improving the performance of the semiconductor integrated circuit. The fin FET is one type of the so-called three-dimensional transistor device having a solid diffusion layer portion. As another type of the three-dimensional transistor device, there is a structure called a nanowire FET, for example.
A delay cell is used for timing adjustment of circuit operation, etc. and implemented using a buffer, for example. Japanese Unexamined Patent Publication No. 2003-60487 describes examples of such a delay adjustment cell.